targets/efinix_t120: use shared Trion DDR integration - #769

Summary

• replace the T120 target-local DDR XML and bus plumbing with the shared LiteX Trion DDR core
• move the board-specific LPDDR3 preset and timing values to the platform
• generate the dedicated 400 MHz DDR clock with the standard Trion PLL helper

This removes 239 lines from the target while preserving the existing hard-controller configuration.

Dependencies

• ram/efinix: add shared Trion DDR integration enjoy-digital/litex#2546
• stacked on targets/efinix: clean up defaults and board integrations #768

Validation

• the generated Efinity DDR XML and pin mapping match the previous implementation
• the complete Efinity target test matrix passes: 10 subtests
• Efinity 2025.1 synthesis, placement, routing, and bitstream generation pass
• the 75 MHz system clock has 2.001 ns setup slack